Advanced Packaging

Advanced packaging refers to combining chips and SMT components into a system-in-package (SiP) application, embedding them in a substrate cavity (embedded PCB), or spreading the contacts of the chip through wafer-level fan-out (WLFO) or panel-level fan-out (PLFO) processes. Our goal is to integrate more functions in a smaller space and bring them to market as quickly as possible.

As the demand for smaller and smaller IIoT devices, sensors, power modules and medical devices increases, more and more manufacturers and industries are discovering the potential of this technology and hope that their manufacturing equipment will have higher performance and productivity. Our ASMPT portfolio of advanced packaging solutions plays an important role.

Advanced Packaging Solutions for Electronics Production

New applications in electronics are driving miniaturization, component density and modularity, while cost pressures are rising. To this end, semiconductor manufacturers and contract manufacturers are increasingly adopting advanced packaging technologies, such as fan-out wafer-level and fan-out panel-level packaging (FOWL/FOPLP), which are increasingly combined with 3D and SiP technologies. This allows them to develop microelectronic technologies with greater functional density and excellent electrical and thermal properties. Advanced packaging technology is extremely complex and requires extreme precision in all process steps. The tight control and optimization of all parameters ensures that quality and yield can be improved to the required level even in a high-volume environment. The only way to achieve this is to use equally accurate and efficient manufacturing equipment.

SiP

It is often said that "data is new oil", so new requirements are put forward for electronic equipment for data collection, communication and analysis. The basis of communication lies in the 5G mobile data network currently under construction, and many devices must be equipped with powerful and highly miniaturized communication modules.

This level of integration is achieved by combining many heterogeneous active and passive components into SiP (System in Package) using technologies such as active embedding or multilayer three-dimensional structures. To enable this process, ASMPT offers a variety of different bare-chip and chip-mount options to meet any of your packaging requirements: from highest-speed chip and SMD combination mount, such as SIPLACE TX micron, to sub-micron bonding, such as AMICRA NANO, and bare-chip and flip-chip combiners.

Embedded

Miniaturization and modularity are the two major trends in semiconductor packaging, and these two trends are still the main driving force to meet the demand for new generation devices after the introduction of 5G, Internet of Things and other mobile devices. Advanced packaging technologies, such as embedded chips that can be handled in large panels that encompass passive and active chips, have emerged as a solution to meet the requirements for greater flexibility, faster time to market, and lower cost.

SIPLACE CA (chip assembly) solutions can handle large thin substrates, place a large number of different types of chips and passive devices in a limited space to meet the expected growth of modules, and achieve higher performance and improve their functionality in a thinner form factor in embedded SIP solutions.

Fan-out

In the past, the semiconductor (especially the back-end packaging business) and SMT production industries operated separately from each other. In advanced packaging, their processes overlap for the first time. The result: In addition to OSAT, traditional electronics manufacturers can also help the semiconductor industry by supplementing their operations to meet the explosive demand for ultra-compact, SMT-capable modules. This opens an attractive growth market for the electronics production industry.

Mounting solutions like SIPLACE CA (chip assembly) support fan-out packaging, combining bare chips with SMT components to form compact wafer-level and panel-level SiP (system-in-package).

In addition to bare-chip and flip-chip combinations, ASMPT also provides complete wafer-level package assembly process solutions-from chip attachment to component inspection, sorting and adhesion.

Power Module

More functions require higher power, and frequently changing loads and high temperatures can cause rapid aging of conductive connections in power electronic devices. One way to solve this problem is to use high temperature resistant materials, such as nano silver paste.

Solution: Through silver sintering, nano-silver particles are shaped to form a stable connection without being melted. DEK Galaxy can easily deposit silver paste. When combined with other ASMPT solutions for silver sintering, chip bonding and wire bonding, component manufacturers can produce more durable IGBTs with better electrical and thermal performance.

The increasing popularity of mobile devices and the Internet of Things (IoT) is driving the need for smaller modules and components. Electronic products must be increasingly integrated and produced to the highest quality standards, but at lower and lower costs.

One way to address these challenges is advanced packaging, which integrates bare or flip chip with SMT components to form ultra-compact systems (system-in-package or SiP). Advanced packaging technology can create complete functional modules, and then these modules can be efficiently and reliably placed on the SMT production line.

Complete process solution